575 search results - page 22 / 115 » Multi-Valued Logic Synthesis |
ERSA
2006
14 years 11 months ago
2006
Abstract-- We have continued development of Optically Reconfigurable Gate Arrays (ORGAs) to realize larger virtual gate count VLSIs than currently available VLSIs. The grain and st...
AICCSA
2007
IEEE
15 years 4 months ago
2007
IEEE
This paper presents an encoding algorithm that is very efficient for many different logic synthesis problems. The algorithm is based on the use of special tables and includes two ...
ICCAD
2010
IEEE
14 years 7 months ago
2010
IEEE
Craig Interpolation is a state-of-the-art technique for logic synthesis and verification, based on Boolean Satisfiability (SAT). Leveraging the efficacy of SAT algorithms, Craig In...
DAC
2002
ACM
15 years 10 months ago
2002
ACM
This paper addresses the problem of automatic generation of implementation software from high-level functional specifications in the context of embedded system on chip designs. So...
GLVLSI
2007
IEEE
15 years 4 months ago
2007
IEEE
A PAL-based logic block is the core of great majority of contemporary CPLD devices. The purpose of the paper is to present a new approach to multi-level synthesis for PAL-based CP...