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ICCAD
1996
IEEE
81views Hardware» more  ICCAD 1996»
15 years 1 months ago
Logic optimization by output phase assignment in dynamic logic synthesis
Ruchir Puri, Andrew Bjorksten, Thomas E. Rosser
71
Voted
ARITH
2009
IEEE
15 years 4 months ago
Challenges in Automatic Optimization of Arithmetic Circuits
Despite the impressive progress of logic synthesis in the past decade, finding the best architecture for a given circuit still remains an open and largely unsolved problem, espec...
Ajay K. Verma, Philip Brisk, Paolo Ienne
76
Voted
GLVLSI
2006
IEEE
124views VLSI» more  GLVLSI 2006»
15 years 3 months ago
Dominator-based partitioning for delay optimization
Most of the logic synthesis algorithms are not scalable for large networks and, for this reason, partitioning is often applied. However traditional mincut-based partitioning techn...
David Bañeres, Jordi Cortadella, Michael Ki...
57
Voted
ASPDAC
2005
ACM
109views Hardware» more  ASPDAC 2005»
14 years 11 months ago
BDD-based two variable sharing extraction
It has been shown that Binary Decision Diagram (BDD) based logic synthesis enjoys faster runtime than the classic logic synthesis systems based on Sum of Product (SOP) form. Howev...
Dennis Wu, Jianwen Zhu