30 search results - page 1 / 6 » Multi-optimization power management for chip multiprocessors |
ISCA
2008
IEEE
15 years 4 months ago
2008
IEEE
Within-die process variation causes individual cores in a Chip Multiprocessor (CMP) to differ substantially in both static power consumed and maximum frequency supported. In this ...
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Voted
IEEEPACT
2008
IEEE
15 years 4 months ago
2008
IEEE
The emergence of power as a first-class design constraint has fueled the proposal of a growing number of run-time power optimizations. Many of these optimizations trade-off power...
ISCA
2009
IEEE
15 years 4 months ago
2009
IEEE
With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boi...
ISLPED
2005
ACM
15 years 3 months ago
2005
ACM
Designers are moving toward chip-multiprocessors (CMPs) to leverage application parallelism for higher performance while keeping design complexity under control. However, to date,...
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...