30 search results - page 3 / 6 » Multi-optimization power management for chip multiprocessors |
145
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PDP
2011
IEEE
14 years 1 months ago
2011
IEEE
—Energy-efficiency is becoming one of the most critical issues in embedded system design. In Network-on-Chip (NoC) based heterogeneous Multiprocessor Systems, the energy consump...
104
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DSN
2007
IEEE
15 years 4 months ago
2007
IEEE
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Exis...
APCSAC
2005
IEEE
15 years 3 months ago
2005
IEEE
Moore’s law describes the growth in on-chip transistor density, which doubles every 18 to 24 months and looks set to continue for at least a decade and possibly longer. This grow...
101
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TCAD
2008
14 years 10 months ago
2008
Three-dimensional integration has the potential to improve the communication latency and integration density of chip-level multiprocessors (CMPs). However, the stacked highpower de...
DSD
2008
IEEE
15 years 4 months ago
2008
IEEE
This paper proposes a system-level cycle-based framework to model and design heterogeneous Multiprocessor Systems on-Chip (MPSoC), called GRAPES. The approach features flexibilit...