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ITC
2002
IEEE
114views Hardware» more  ITC 2002»
15 years 10 months ago
Scan Power Reduction Through Test Data Transition Frequency Analysis
Significant reductions in test application times can be achieved through parallelizing core tests; however, simultaneous test of various cores may result in exceeding power thres...
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailog...
FMICS
2006
Springer
15 years 9 months ago
Model-Based Testing of a WAP Gateway: An Industrial Case-Study
Abstract. We present experiences from a case study where a model-based approach to black-box testing is applied to verify that a Wireless Application Protocol (WAP) gateway conform...
Anders Hessel, Paul Pettersson
GLVLSI
2007
IEEE
189views VLSI» more  GLVLSI 2007»
15 years 12 months ago
Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems
The path-delay fault simulation of functional tests on complex circuits such as current processor-based systems is a daunting task. The amount of computing power and memory needed...
Paolo Bernardi, Michelangelo Grosso, Matteo Sonza ...
ENTCS
2010
99views more  ENTCS 2010»
15 years 5 months ago
State Based Robustness Testing for Components
Component based development allows to build software upon existing components and promises to improve software reuse and reduce costs. To gain reliability of a component based sys...
Bin Lei, Zhiming Liu, Charles Morisset, Xuandong L...
VL
2005
IEEE
119views Visual Languages» more  VL 2005»
15 years 11 months ago
How Well Do Professional Developers Test with Code Coverage Visualizations? An Empirical Study
Despite years of availability of testing tools, professional software developers still seem to need better support to determine the effectiveness of their tests. Without improveme...
Joseph Lawrance, Steven Clarke, Margaret M. Burnet...