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ICPADS
2006
IEEE
15 years 3 months ago
Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture
The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new...
Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edw...
SIGSOFT
2010
ACM
14 years 7 months ago
Building scalable software systems in the multicore era
Software systems must face two challenges today: growing complexity and increasing parallelism in the underlying computational models. The problem of increased complexity is often...
Hridesh Rajan
ICCD
2007
IEEE
205views Hardware» more  ICCD 2007»
15 years 6 months ago
Hardware libraries: An architecture for economic acceleration in soft multi-core environments
In single processor architectures, computationallyintensive functions are typically accelerated using hardware accelerators, which exploit the concurrency in the function code to ...
David Meisner, Sherief Reda
IWOMP
2009
Springer
15 years 4 months ago
A Proposal to Extend the OpenMP Tasking Model for Heterogeneous Architectures
Abstract. OpenMP has evolved recently towards expressing unstructured parallelism, targeting the parallelization of a broader range of applications in the current multicore era. Ho...
Eduard Ayguadé, Rosa M. Badia, Daniel Cabre...
IEEEPACT
2006
IEEE
15 years 3 months ago
Core architecture optimization for heterogeneous chip multiprocessors
Previous studies have demonstrated the advantages of single-ISA heterogeneous multi-core architectures for power and performance. However, none of those studies examined how to de...
Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi