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ICCAD
1995
IEEE
134views Hardware» more  ICCAD 1995»
15 years 6 months ago
A delay model for logic synthesis of continuously-sized networks
ng certain electrical noise and power constraints.Abstract: We present a new delay model for use in logic synthesis. A traditional model treats the area of a library cell as consta...
Joel Grodstein, Eric Lehman, Heather Harkness, Bil...
LCN
2005
IEEE
15 years 8 months ago
Implementation and Performance Analysis of a Packet Scheduler on a Programmable Network Processor
— The problem of achieving fairness in the allocation of the bandwidth resource on a link shared by multiple flows of traffic has been extensively researched over the last deca...
Fariza Sabrina, Salil S. Kanhere, Sanjay Jha
MOBICOM
2012
ACM
13 years 5 months ago
Faster GPS via the sparse fourier transform
GPS is one of the most widely used wireless systems. A GPS receiver has to lock on the satellite signals to calculate its position. The process of locking on the satellites is qui...
Haitham Hassanieh, Fadel Adib, Dina Katabi, Piotr ...
MONET
2008
150views more  MONET 2008»
15 years 3 months ago
A Multi-radio 802.11 Mesh Network Architecture
Routers equipped with multiple 802.11 radios can alleviate capacity problems in wireless mesh networks. However, a practical, complete system architecture that can realize the bene...
Krishna N. Ramachandran, Irfan Sheriff, Elizabeth ...
MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
15 years 1 months ago
Throughput-Effective On-Chip Networks for Manycore Accelerators
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
Ali Bakhoda, John Kim, Tor M. Aamodt