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PLDI
1999
ACM
15 years 1 months ago
Cache-Conscious Structure Layout
Hardware trends have produced an increasing disparity between processor speeds and memory access times. While a variety of techniques for tolerating or reducing memory latency hav...
Trishul M. Chilimbi, Mark D. Hill, James R. Larus
BMCBI
2007
168views more  BMCBI 2007»
14 years 9 months ago
Benchmarking consensus model quality assessment for protein fold recognition
Background: Selecting the highest quality 3D model of a protein structure from a number of alternatives remains an important challenge in the field of structural bioinformatics. M...
Liam J. McGuffin
IEEEARES
2010
IEEE
14 years 7 months ago
Using Smart Cards for Tamper-Proof Timestamps on Untrusted Clients
Online auctions of governmental bonds and CO2 certificates are challenged by high availability requirements in face of high peak loads around the auction deadline. Traditionally, t...
Guenther Starnberger, Lorenz Froihofer, Karl M. G&...
BMCBI
2010
161views more  BMCBI 2010»
14 years 7 months ago
LTC: a novel algorithm to improve the efficiency of contig assembly for physical mapping in complex genomes
Background: Physical maps are the substrate of genome sequencing and map-based cloning and their construction relies on the accurate assembly of BAC clones into large contigs that...
Zeev Frenkel, Etienne Paux, David I. Mester, Cathe...
ISQED
2006
IEEE
107views Hardware» more  ISQED 2006»
15 years 3 months ago
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
Li-Chung Hsu, Hung-Ming Chen