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TCAD
1998
82views more  TCAD 1998»
14 years 11 months ago
LOT: Logic Optimization with Testability. New transformations for logic synthesis
—A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random...
Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang K...
90
Voted
ASPDAC
2004
ACM
85views Hardware» more  ASPDAC 2004»
15 years 3 months ago
Multi-level placement with circuit schema based clustering in analog IC layouts
This paper aims at developing an automated device-level placement for analog circuit design which achieves comparable quality to manual designs by experts. It extracts a set of cl...
Takashi Nojima, Xiaoke Zhu, Yasuhiro Takashima, Sh...
ISPD
2005
ACM
151views Hardware» more  ISPD 2005»
15 years 5 months ago
Multilevel generalized force-directed method for circuit placement
Automatic circuit placement has received renewed interest recently given the rapid increase of circuit complexity, increase of interconnect delay, and potential sub-optimality of ...
Tony F. Chan, Jason Cong, Kenton Sze
ICCAD
2003
IEEE
141views Hardware» more  ICCAD 2003»
15 years 5 months ago
An Enhanced Multilevel Algorithm for Circuit Placement
This paper presents several important enhancements to the recently published multilevel placement package mPL [12]. The improvements include (i) unconstrained quadratic relaxation...
Tony F. Chan, Jason Cong, Tim Kong, Joseph R. Shin...