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VLSID
2003
IEEE
126views VLSI» more  VLSID 2003»
15 years 10 months ago
Comparison of Heuristic Algorithms for Variable Partitioning in Circuit Implementation
Functional decomposition is a process of splitting a complex circuit into smaller sub-circuits. This paper deals with the problem of determining the set of best free and bound var...
Muthukumar Venkatesan, Henry Selvaraj
ICCAD
2002
IEEE
100views Hardware» more  ICCAD 2002»
15 years 6 months ago
Multi-objective circuit partitioning for cutsize and path-based delay minimization
– In this paper we present multi-objective hMetis partitioning for simultaneous cutsize and circuit delay minimization. We change the partitioning process itself by introducing a...
Cristinel Ababei, Navaratnasothie Selvakkumaran, K...
IPPS
1998
IEEE
15 years 1 months ago
Meta-heuristics for Circuit Partitioning in Parallel Test Generation
In this communication Simulated Annealing and Genetic Algorithms, are applied to the graph partitioning problem. These techniques mimic processes in statistical mechanics and biol...
Consolación Gil, Julio Ortega, Antonio F. D...
ASPDAC
2005
ACM
92views Hardware» more  ASPDAC 2005»
14 years 11 months ago
Partitioning and placement for buildable QCA circuits
— Quantum-dot Cellular Automata (QCA) is a novel computing mechanism that can represent binary information based on spatial distribution of electron charge configuration in chem...
Ramprasad Ravichandran, Michael T. Niemier, Sung K...
VLSID
2002
IEEE
115views VLSI» more  VLSID 2002»
15 years 10 months ago
A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits
We describe a built-in test pattern generation method for scan circuits. The method is based on partitioning and storage of test sets. Under this method, a precomputed test set is...
Irith Pomeranz, Sudhakar M. Reddy