395 search results - page 21 / 79 » Multilevel Circuit Partitioning |
ASPDAC
2006
ACM
15 years 3 months ago
2006
ACM
This paper advances a new methodology based on signal-path information to resolve the problem of device-level placement for analog layout. This methodology is mainly based on three...
85
Voted
GECCO
2004
Springer
15 years 3 months ago
2004
Springer
We propose a hybrid genetic algorithm for partitioning a VLSI circuit graph into two disjoint graphs of minimum cut size. The algorithm includes a local optimization heuristic whic...
ASPDAC
2000
ACM
15 years 1 months ago
2000
ACM
We present a satisfiability based multi-clock path analysis method. The method uses propositional satisfiability (SAT) in the detection of multi-clock paths. We show a method to re...
AICCSA
2005
IEEE
15 years 3 months ago
2005
IEEE
ASPDAC
1999
ACM
15 years 2 months ago
1999
ACM
