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DSD
2007
IEEE
87views Hardware» more  DSD 2007»
15 years 4 months ago
On the Construction of Small Fully Testable Circuits with Low Depth
During synthesis of circuits for Boolean functions area, delay and testability are optimization goals that often contradict each other. Multi-level circuits are often quite small ...
Görschwin Fey, Anna Bernasconi, Valentina Cir...
ASPDAC
1999
ACM
132views Hardware» more  ASPDAC 1999»
15 years 2 months ago
Faster and Better Spectral Algorithms for Multi-Way Partitioning
In this paper, two faster and better spectral algorithms are presented for the multi-way circuit partitioning problem with the objective of minimizing the Scaled Cost. As pointed ...
Jan-Yang Chang, Yu-Chen Liu, Ting-Chi Wang
DAC
1994
ACM
15 years 1 months ago
Acyclic Multi-Way Partitioning of Boolean Networks
Acyclic partitioning on combinational boolean networks has wide range of applications, from multiple FPGA chip partitioning to parallel circuit simulation. In this paper, we prese...
Jason Cong, Zheng Li, Rajive Bagrodia
DFT
2005
IEEE
64views VLSI» more  DFT 2005»
15 years 3 months ago
Implementation of Concurrent Checking Circuits by Independent Sub-circuits
The present paper proposes a new method for detecting arbitrary faults in a functional circuit when the set of codewords is limited and known in advance. The method is based on im...
Vladimir Ostrovsky, Ilya Levin
ICAPR
2005
Springer
15 years 3 months ago
Weighted Adaptive Neighborhood Hypergraph Partitioning for Image Segmentation
Abstract. The aim of this paper is to present an improvement of a previously published algorithm. The proposed approach is performed in two steps. In the first step, we generate t...
Soufiane Rital, Hocine Cherifi, Serge Miguet