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» Multilevel Circuit Partitioning
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63
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DATE
2005
IEEE
105views Hardware» more  DATE 2005»
15 years 3 months ago
An Improved Multi-Level Framework for Force-Directed Placement
One of the greatest impediments to achieving high quality placements using force-directed methods lies in the large amount of overlap initially present in these techniques. This o...
Kristofer Vorwerk, Andrew A. Kennings
BIBE
2005
IEEE
14 years 11 months ago
A Multi-Level Approach to SCOP Fold Recognition
The classification of proteins based on their structure can play an important role in the deduction or discovery of protein function. However, the relatively low number of solved...
Keith Marsolo, Srinivasan Parthasarathy, Chris H. ...
ICCD
2006
IEEE
116views Hardware» more  ICCD 2006»
15 years 6 months ago
RTL Scan Design for Skewed-Load At-speed Test under Power Constraints
This paper discusses an automated method to build scan chains at the register-transfer level (RTL) for powerconstrained at-speed testing. By analyzing a circuit at the RTL, where ...
Ho Fai Ko, Nicola Nicolici
ICCD
2008
IEEE
139views Hardware» more  ICCD 2008»
15 years 6 months ago
Probabilistic error propagation in logic circuits using the Boolean difference calculus
- A gate level probabilistic error propagation model is presented which takes as input the Boolean function of the gate, the signal and error probabilities of the gate inputs, and ...
Nasir Mohyuddin, Ehsan Pakbaznia, Massoud Pedram
75
Voted
CODES
1996
IEEE
15 years 1 months ago
A Multi-Level Transformation Approach to HW/SW Codesign: A Case Study
This reported work applies a transformational synthesis approach to hardware/software codesign. In this approach, the process of algorithm design is coupled early on with hardware...
Tommy King-Yin Cheung, Graham R. Hellestrand, Pras...