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ISPD
1999
ACM
98views Hardware» more  ISPD 1999»
15 years 2 months ago
Towards synthetic benchmark circuits for evaluating timing-driven CAD tools
For the development and evaluation of CAD-tools for partitioning, floorplanning, placement, and routing of digital circuits, a huge amount of benchmark circuits with suitable cha...
Dirk Stroobandt, Peter Verplaetse, Jan Van Campenh...
SC
2009
ACM
15 years 4 months ago
Bridging parallel and reconfigurable computing with multilevel PGAS and SHMEM+
Reconfigurable computing (RC) systems based on FPGAs are becoming an increasingly attractive solution to building parallel systems of the future. Applications targeting such syste...
Vikas Aggarwal, Alan D. George, K. Yalamanchili, C...
MP
1998
117views more  MP 1998»
14 years 9 months ago
The node capacitated graph partitioning problem: A computational study
In this paper we consider the problem of ^-partitioning the nodes of a graph with capacity restrictions on the sum of the node weights in each subset of the partition, and the obje...
Carlos Eduardo Ferreira, Alexander Martin, C. Carv...
89
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ICDCS
2011
IEEE
13 years 9 months ago
Economical and Robust Provisioning of N-Tier Cloud Workloads: A Multi-level Control Approach
—Resource provisioning for N-tier web applications in Clouds is non-trivial due to at least two reasons. First, there is an inherent optimization conflict between cost of resour...
PengCheng Xiong, Zhikui Wang, Simon Malkowski, Qin...
ISPD
2006
ACM
175views Hardware» more  ISPD 2006»
15 years 3 months ago
mPL6: enhanced multilevel mixed-size placement
The multilevel placement package mPL6 combines improved implementations of the global placer mPL5 (ISPD05) and the XDP legalizer and detailed placer (ASPDAC06). It consistently pr...
Tony F. Chan, Jason Cong, Joseph R. Shinnerl, Kent...