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ICCD
2005
IEEE
101views Hardware» more  ICCD 2005»
15 years 6 months ago
Three-Dimensional Cache Design Exploration Using 3DCacti
As technology scales, interconnects dominate the performance and power behavior of deep submicron designs. Three-dimensional integrated circuits (3D ICs) have been proposed as a w...
Yuh-Fang Tsai, Yuan Xie, Narayanan Vijaykrishnan, ...
DAC
1997
ACM
15 years 1 months ago
A Graph-Based Synthesis Algorithm for AND/XOR Networks
In this paper, we introduce a Shared Multiple Rooted XORbased Decomposition Diagram XORDD to represent functions with multiple outputs. Based on the XORDD representation, we dev...
Yibin Ye, Kaushik Roy
ICCAD
1996
IEEE
87views Hardware» more  ICCAD 1996»
15 years 1 months ago
Partitioned ROBDDs - a compact, canonical and efficiently manipulable representation for Boolean functions
We presenta new representationfor Boolean functions called PartitionedROBDDs. In this representation we divide the Boolean space into `k' partitions and represent a function ...
Amit Narayan, Jawahar Jain, Masahiro Fujita, Alber...
DAC
1995
ACM
15 years 1 months ago
Multi-way Partitioning for Minimum Delay for Look-Up Table Based FPGAs
In this paper we present a set cover based approach (SCP) to multi-way partitioning for minimum delay for Look-Up Table based FPGAs. SCP minimizes the number of chip-crossings on ...
Prashant Sawkar, Donald E. Thomas
ISCAS
2008
IEEE
115views Hardware» more  ISCAS 2008»
15 years 4 months ago
FSMD partitioning for low power using simulated annealing
— It is well known that significant power savings can be obtained by disabling or shutting down parts of a circuit during idle periods. One method is to use a high level partiti...
Nainesh Agarwal, Nikitas J. Dimopoulos