395 search results - page 38 / 79 » Multilevel Circuit Partitioning |
69
Voted
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
Soft errors are an increasingly serious problem for logic circuits. To estimate the effects of soft errors on such circuits, we develop a general computational framework based on ...
ISPD
1999
ACM
15 years 2 months ago
1999
ACM
The presence of fixed terminals in hypergraph partitioning instances arising in top-down standard-cell placement makes such instances qualitatively different from the free hyperg...
MASCOTS
2001
14 years 11 months ago
2001
This paper uses trace-driven simulations to evaluate the performance of different cache management techniques for multi-level Web proxy caching hierarchies. In particular, the exp...
ISCAS
2007
IEEE
15 years 4 months ago
2007
IEEE
— Discrete wavelet transform (DWT) has been shown to provide exceptionally efficient data compression for neural records. This paper describes an area-power minimized hardware im...
GLVLSI
2005
IEEE
15 years 3 months ago
2005
IEEE
In this paper we develop a theory of equivalence checking (EC) and logic synthesis of circuits with a common specification (CS). We show that two combinational circuits N1, N2 have...