395 search results - page 39 / 79 » Multilevel Circuit Partitioning |
ACSD
2010
IEEE
14 years 7 months ago
2010
IEEE
Digital components play a central role in the design of complex embedded systems. These components are interconnected with other, possibly analog, devices and the physical environm...
ASPDAC
2004
ACM
15 years 3 months ago
2004
ACM
Abstract— This paper presents a power grid analyzer that combines a divide-and-conquer strategy with a random-walk engine. A single-level hierarchical method is first described ...
ISQED
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper is concerned with statically analyzing the susceptibility of arbitrary combinational circuits to single event upsets that are becoming a significant concern for reliabi...
DAC
1994
ACM
15 years 1 months ago
1994
ACM
A low overhead DFT technique, called clock-grouping, for delay testing of sequential synchronous circuits is presented. The proposed technique increases robust path delay fault co...
ASPDAC
2008
ACM
14 years 11 months ago
2008
ACM
In this paper, we propose a new model order reduction approach for large interconnect circuits using hierarchical decomposition and Krylov subspace projection-based model order re...