395 search results - page 42 / 79 » Multilevel Circuit Partitioning |
ICCAD
2005
IEEE
15 years 6 months ago
2005
IEEE
Heat dissipation is one of the most serious challenges in 3D IC designs. One effective way of reducing circuit temperature is to introduce thermal through-the-silicon (TTS) vias....
FPGA
1997
ACM
15 years 1 months ago
1997
ACM
We present a general approach to the FPGA technology mapping problem that applies to any logic block composed of lookup tables LUTs and can yield optimal solutions. The connecti...
IPPS
2010
IEEE
14 years 7 months ago
2010
IEEE
This paper focuses on parallelization of the classic static timing analysis (STA) algorithm for verifying timing characteristics of digital integrated circuits. Given ever-increasi...
IPPS
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper presents an efficient modeling scheme and a partitioning heuristic for parallelizing VLSI post-placement timing optimization. Encoding the paths with timing violations...
DATE
2002
IEEE
15 years 2 months ago
2002
IEEE
In this paper, we show that under the constant delay model the placement problem is equivalent to minimizing a weighted sum of wire lengths. The weights can be efficiently compute...