395 search results - page 49 / 79 » Multilevel Circuit Partitioning |
CDES
2006
14 years 11 months ago
2006
A neural network approach is presented for modeling and characterization of on-chip copper spiral inductors. The approach involves the creation of neural network models to map 3D ...
ISPD
2005
ACM
15 years 3 months ago
2005
ACM
In this paper, we develop a mixed-size placement tool, Dragon2005, to solve large scale placement problems effectively. A top-down hierarchical approach based on min-cut partition...
VLSID
2002
IEEE
15 years 10 months ago
2002
IEEE
IDDQ testing has been used as a test technique to supplement voltage testing of CMOS chips. The idea behind IDDQ testing is to declare a chip as faulty if the steady-state current...
ICCAD
2007
IEEE
15 years 4 months ago
2007
IEEE
This paper presents fully parallel domain decomposition (DD) techniques for efficient simulation of large-scale linear circuits such as power grids. DD techniques that use non-ov...
ISCAS
1999
IEEE
15 years 2 months ago
1999
IEEE
An FPGA-based reconfigurable system may contain boards of FPGAs which are reconfigured for different applications and must work correctly. This paper presents a novel approach for...