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ISPD
2005
ACM
116views Hardware» more  ISPD 2005»
15 years 3 months ago
A fast algorithm for power grid design
This paper presents an efficient heuristic algorithm to design a power distribution network of a chip by employing a successive partitioning and grid refinement scheme. In an it...
Jaskirat Singh, Sachin S. Sapatnekar
ICCAD
2006
IEEE
119views Hardware» more  ICCAD 2006»
15 years 6 months ago
Post-placement voltage island generation
High power consumption will shorten battery life for handheld devices and cause thermal and reliability problems. One way to lower the dynamic power consumption is to reduce the s...
Royce L. S. Ching, Evangeline F. Y. Young, Kevin C...
VLSID
2001
IEEE
129views VLSI» more  VLSID 2001»
15 years 10 months ago
Design Of Provably Correct Storage Arrays
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann
PATMOS
2004
Springer
15 years 3 months ago
Leakage Power Analysis and Comparison of Deep Submicron Logic Gates
Basic combinational gates, including NAND, NOR and XOR, are fundamental building blocks in CMOS digital circuits. This paper analyses and compares the power consumption due to tran...
Geoff V. Merrett, Bashir M. Al-Hashimi
ITC
2003
IEEE
134views Hardware» more  ITC 2003»
15 years 3 months ago
Effectiveness Improvement of ECR Tests
Energy Consumption Ratio (ECR) test, a current-based test, has shown its ability to reduce the impact of process variations and detect hard-to-detect faults. The effectiveness of ...
Wanli Jiang, Erik Peterson, Bob Robotka