Sciweavers

395 search results - page 60 / 79
» Multilevel Circuit Partitioning
Sort
View
DAC
2000
ACM
15 years 10 months ago
Can recursive bisection alone produce routable placements?
This work focuses on congestion-driven placement of standard cells into rows in the fixed-die context. We summarize the stateof-the-art after two decades of research in recursive ...
Andrew E. Caldwell, Andrew B. Kahng, Igor L. Marko...
VLSID
2008
IEEE
138views VLSI» more  VLSID 2008»
15 years 10 months ago
Memory Architecture Exploration Framework for Cache Based Embedded SOC
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...
FCCM
2005
IEEE
139views VLSI» more  FCCM 2005»
15 years 3 months ago
A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation
Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously in...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
ICCAD
2001
IEEE
111views Hardware» more  ICCAD 2001»
15 years 6 months ago
Congestion Aware Layout Driven Logic Synthesis
In this paper, we present novel algorithms that effectively combine physical layout and early logic synthesis to improve overall design quality. In addition, we employ partitionin...
Thomas Kutzschebauch, Leon Stok
IMR
2005
Springer
15 years 3 months ago
An Interior Surface Generation Method for All-Hexahedral Meshing
This paper describes an interior surface generation method and a strategy for all-hexahedral mesh generation. It is well known that a solid homeomorphic to a ball with even number...
Tatsuhiko Suzuki, Shigeo Takahashi, Jason Shepherd