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TVLSI
2002
130views more  TVLSI 2002»
14 years 11 months ago
Incremental compilation for parallel logic verification systems
Although simulation remains an important part of application-specific integrated circuit (ASIC) validation, hardware-assisted parallel verification is becoming a larger part of the...
R. Tessier, S. Jana
ICCD
2005
IEEE
116views Hardware» more  ICCD 2005»
15 years 8 months ago
Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis
Consideration of pairs of transition in probabilistic simulation allows power estimation for digital circuits in which inertial delays can filter glitches [5]. However, the merit ...
Fei Hu, Vishwani D. Agrawal
DATE
2007
IEEE
73views Hardware» more  DATE 2007»
15 years 6 months ago
Design methods for security and trust
The design of ubiquitous and embedded computers focuses on cost factors such as area, power-consumption, and performance. Security and trust properties, on the other hand, are oft...
Ingrid Verbauwhede, Patrick Schaumont
DATE
2007
IEEE
85views Hardware» more  DATE 2007»
15 years 6 months ago
Low-power warp processor for power efficient high-performance embedded systems
Researchers previously proposed warp processors, a novel architecture capable of transparently optimizing an executing application by dynamically re-implementing critical kernels ...
Roman L. Lysecky
ETS
2006
IEEE
119views Hardware» more  ETS 2006»
15 years 5 months ago
On-Chip Test Generation Using Linear Subspaces
A central problem in built-in self test (BIST) is how to efficiently generate a small set of test vectors that detect all targeted faults. We propose a novel solution that uses l...
Ramashis Das, Igor L. Markov, John P. Hayes