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GLVLSI
2006
IEEE
142views VLSI» more  GLVLSI 2006»
15 years 3 months ago
Dynamic instruction schedulers in a 3-dimensional integration technology
We present the design of high-performance and energy-efficient dynamic instruction schedulers in a 3-Dimensional integration technology. Based on a previous observation that the c...
Kiran Puttaswamy, Gabriel H. Loh
84
Voted
DAC
2006
ACM
15 years 3 months ago
Automated design of pin-constrained digital microfluidic arrays for lab-on-a-chip applications*
Microfluidics-based biochips, also referred to as lab-on-a-chip (LoC), are devices that integrate fluid-handling functions such as sample preparation, analysis, separation, and de...
William L. Hwang, Fei Su, Krishnendu Chakrabarty
SAMOS
2004
Springer
15 years 3 months ago
High-Speed Event-Driven RTL Compiled Simulation
In this paper we present a new approach for generating high-speed optimized event-driven register transfer level (RTL) compiled simulators. The generation of the simulators is part...
Alexey Kupriyanov, Frank Hannig, Jürgen Teich
DATE
2003
IEEE
124views Hardware» more  DATE 2003»
15 years 2 months ago
Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration
– Floorplanning large designs with many hard macros and IP blocks of various sizes is becoming an increasingly important and challenging problem. This paper presents a global flo...
Wonjoon Choi, Kia Bazargan
ICNP
2003
IEEE
15 years 2 months ago
Packet Classification Using Extended TCAMs
CAMs are the most popular practical method for implementing packet classification in high performance routers. Their principal drawbacks are high power consumption and inefficient...
Ed Spitznagel, David E. Taylor, Jonathan S. Turner