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CEC
2009
IEEE
15 years 4 months ago
Task decomposition and evolvability in intrinsic evolvable hardware
— Many researchers have encountered the problem that the evolution of electronic circuits becomes exponentially more difficult when problems with an increasing number of outputs...
Tüze Kuyucu, Martin Trefzer, Julian Francis M...
ISPD
2005
ACM
205views Hardware» more  ISPD 2005»
15 years 3 months ago
Coupling aware timing optimization and antenna avoidance in layer assignment
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...
Di Wu, Jiang Hu, Rabi N. Mahapatra
ASPDAC
2006
ACM
148views Hardware» more  ASPDAC 2006»
15 years 1 months ago
TAPHS: thermal-aware unified physical-level and high-level synthesis
Thermal effects are becoming increasingly important during integrated circuit design. Thermal characteristics influence reliability, power consumption, cooling costs, and performan...
Zhenyu (Peter) Gu, Yonghong Yang, Jia Wang, Robert...
TCAD
1998
86views more  TCAD 1998»
14 years 9 months ago
Fast heuristic and exact algorithms for two-level hazard-free logic minimization
None of the available minimizers for 2-level hazard-free logic minimization can synthesize very large circuits. This limitation has forced researchers to resort to manual and auto...
Michael Theobald, Steven M. Nowick
ASPDAC
2010
ACM
637views Hardware» more  ASPDAC 2010»
14 years 7 months ago
A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography
As Double Patterning Lithography(DPL) becomes the leading candidate for sub-30nm lithography process, we need a fast and lithography friendly decomposition framework. In this pape...
Jae-Seok Yang, Katrina Lu, Minsik Cho, Kun Yuan, D...