395 search results - page 9 / 79 » Multilevel Circuit Partitioning |
PARA
2000
Springer
15 years 1 months ago
2000
Springer
JPDC
2008
14 years 9 months ago
2008
JPDC
1998
14 years 9 months ago
1998
GECCO
2005
Springer
15 years 3 months ago
2005
Springer
The clock signal and clock skew become more and more important for the circuit performance. Since there are salient shortcomings in the conventional topology construction algorith...
ICCAD
1995
IEEE
15 years 1 months ago
1995
IEEE
: A new approach to optimize multi-level logic circuits is introduced. Given a multi-level circuit, the synthesis method optimizes its area, simultaneously enhancing its random pat...