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DAC
2003
ACM
15 years 10 months ago
Analog and RF circuit macromodels for system-level analysis
Design and validation of mixed-signal integrated systems require evel model abstractions. Generalized Volterra series based models have been successfully applied for analog and RF...
Xin Li, Peng Li, Yang Xu, Lawrence T. Pileggi
GLVLSI
2007
IEEE
158views VLSI» more  GLVLSI 2007»
14 years 11 months ago
RT-level vector selection for realistic peak power simulation
We present a vector selection methodology for estimating the peak power dissipation in a CMOS logic circuit. The ultimate goal is to combine the speed of RT-level simulation with ...
Chia-Chien Weng, Ching-Shang Yang, Shi-Yu Huang
77
Voted
DAC
2009
ACM
15 years 10 months ago
Event-driven gate-level simulation with GP-GPUs
Logic simulation is a critical component of the design tool flow in modern hardware development efforts. It is used widely ? from high-level descriptions down to gate-level ones ?...
Debapriya Chatterjee, Andrew DeOrio, Valeria Berta...
69
Voted
JMLR
2010
112views more  JMLR 2010»
14 years 4 months ago
Reduced-Rank Hidden Markov Models
Hsu et al. (2009) recently proposed an efficient, accurate spectral learning algorithm for Hidden Markov Models (HMMs). In this paper we relax their assumptions and prove a tighte...
Sajid M. Siddiqi, Byron Boots, Geoffrey J. Gordon
DATE
2003
IEEE
124views Hardware» more  DATE 2003»
15 years 2 months ago
Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration
– Floorplanning large designs with many hard macros and IP blocks of various sizes is becoming an increasingly important and challenging problem. This paper presents a global flo...
Wonjoon Choi, Kia Bazargan