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DATE
2004
IEEE
157views Hardware» more  DATE 2004»
15 years 1 months ago
Hierarchical Modeling and Simulation of Large Analog Circuits
This paper proposes a new hierarchical circuit modeling and simulation technique in s-domain for linear analog circuits. The new algorithm can perform circuit complexity reduction...
Sheldon X.-D. Tan, Zhenyu Qi, Hang Li
GLVLSI
2010
IEEE
156views VLSI» more  GLVLSI 2010»
15 years 2 months ago
A multi-level approach to reduce the impact of NBTI on processor functional units
NBTI is one of the most important silicon reliability problems facing processor designers today. The impact of NBTI can be mitigated at both the circuit and microarchitecture leve...
Taniya Siddiqua, Sudhanva Gurumurthi
COMPUTING
2008
174views more  COMPUTING 2008»
14 years 9 months ago
Multilevel algorithms for Rannacher-Turek finite element approximation of 3D elliptic problems
Generalizing the approach of a previous work [15] the authors present multilevel preconditioners for three-dimensional (3D) elliptic problems discretized by a family of Rannacher ...
Ivan Georgiev, Johannes Kraus, Svetozar Margenov
ATAL
2009
Springer
15 years 4 months ago
Towards multi-level modeling of self-assembling intelligent micro-systems
We investigate and model the dynamics of two-dimensional stochastic self-assembly of intelligent micro-systems with minimal requirements in terms of sensing, actuation, and contro...
Grégory Mermoud, Juergen Brugger, Alcherio ...
ICCAD
2005
IEEE
117views Hardware» more  ICCAD 2005»
15 years 6 months ago
IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs
Abstract— We present in this paper a new interconnect-driven multilevel floorplanning, called IMF, to handle large-scale building-module designs. Unlike the traditional multilev...
Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin