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RTS
2006
129views more  RTS 2006»
14 years 10 months ago
Modeling out-of-order processors for WCET analysis
Estimating the Worst Case Execution Time (WCET) of a program on a given processor is important for the schedulability analysis of real-time systems. WCET analysis techniques typic...
Xianfeng Li, Abhik Roychoudhury, Tulika Mitra
DATE
2003
IEEE
137views Hardware» more  DATE 2003»
15 years 3 months ago
Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs
We present two novel strategies to increase the scope for application of speculative code motions: (1) Adding scheduling steps dynamically during scheduling to conditional branche...
Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexa...
ISCA
2002
IEEE
95views Hardware» more  ISCA 2002»
15 years 3 months ago
Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor
This paper presents the Alpha EV8 conditional branch predictor. The Alpha EV8 microprocessor project, canceled in June 2001 in a late phase of development, envisioned an aggressiv...
André Seznec, Stephen Felix, Venkata Krishn...
ICMCS
2005
IEEE
187views Multimedia» more  ICMCS 2005»
15 years 3 months ago
A 3D Predict Hexagon Search Algorithm for Fast Block Motion Estimation on H.264 Video Coding
In the upcoming video coding standard, MPEG-4 AVC/JVT/H.264, motion estimation is allowed to use multiple references and multiple block sizes to improve the rate-distortion perfor...
Tsung-Han Tsai, Yu-Nan Pan
ISCA
2003
IEEE
108views Hardware» more  ISCA 2003»
15 years 3 months ago
Effective ahead Pipelining of Instruction Block Address Generation
On a N-way issue superscalar processor, the front end instruction fetch engine must deliver instructions to the execution core at a sustained rate higher than N instructions per c...
André Seznec, Antony Fraboulet