126 search results - page 14 / 26 » Multiple FPGA Partitioning with Performance Optimization |
60
Voted
DATE
2007
IEEE
15 years 4 months ago
2007
IEEE
Researchers previously proposed warp processors, a novel architecture capable of transparently optimizing an executing application by dynamically re-implementing critical kernels ...
ERSA
2006
14 years 11 months ago
2006
Abstract-- With the constantly increasing gate capacity of FPGAs, a single FPGA chip is able to employ large-scale applications. To connect a large number of computational nodes, N...
ISPAN
1997
IEEE
15 years 1 months ago
1997
IEEE
This paper presents a strategy for efficiently rendering time-varying volume data on a distributed-memory parallel computer. Visualizing time-varying volume data take both large s...
ASAP
2008
IEEE
15 years 4 months ago
2008
IEEE
As semiconductor processing technology continues to scale down, managing reliability becomes an increasingly difficult challenge in high-performance microprocessor design. Transie...
ISLPED
2000
ACM
15 years 2 months ago
2000
ACM
Memory-processor integration o ers new opportunities for reducing the energy of a system. In the case of embedded systems, one solution consists of mapping the most frequently acc...