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» Multiple FPGA Partitioning with Performance Optimization
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DAC
2003
ACM
15 years 10 months ago
Dynamic hardware/software partitioning: a first approach
Partitioning an application among software running on a microprocessor and hardware co-processors in on-chip configurable logic has been shown to improve performance and energy co...
Greg Stitt, Roman L. Lysecky, Frank Vahid
ICC
2007
IEEE
118views Communications» more  ICC 2007»
15 years 3 months ago
Single and Multiple Parameters Sensitivity Study of Location Management Area Partitioning for GSM Networks
–- To obtain optimal location area (LA) partitioning in cellular radio networks is important since it maximizes the usable bandwidth to support services. However, we feel that th...
Yong Huat Chew, Boon Sain Yeo, Daniel Chien Ming K...
DATE
2007
IEEE
114views Hardware» more  DATE 2007»
15 years 3 months ago
Two-level microprocessor-accelerator partitioning
The integration of microprocessors and field-programmable gate array (FPGA) fabric on a single chip increases both the utility and necessity of tools that automatically move softw...
Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank V...
FCCM
2007
IEEE
117views VLSI» more  FCCM 2007»
15 years 3 months ago
FPGA Acceleration of Gene Rearrangement Analysis
In this paper we present our work toward FPGA acceleration of phylogenetic reconstruction, a type of analysis that is commonly performed in the fields of systematic biology and co...
Jason D. Bakos
FCCM
2006
IEEE
144views VLSI» more  FCCM 2006»
15 years 3 months ago
Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA
In this paper, we investigate a combination of two techniques — instruction coding and instruction re-ordering — for optimizing energy in embedded processor control. We presen...
Robert G. Dimond, Oskar Mencer, Wayne Luk