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» Multiple Faults: Modeling, Simulation and Test
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EH
2005
IEEE
171views Hardware» more  EH 2005»
15 years 3 months ago
Implementation Results for a Fault-Tolerant Multicellular Architecture Inspired by Endocrine Communication
The hybrid redundancy structure found at the cellular level of higher animals provides complex organism with the three key features of a reliability-engineered system: fault toler...
Andrew J. Greensted, Andy M. Tyrrell
EVOW
2001
Springer
15 years 2 months ago
ARPIA: A High-Level Evolutionary Test Signal Generator
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda...
DATE
2007
IEEE
123views Hardware» more  DATE 2007»
15 years 3 months ago
Clock domain crossing fault model and coverage metric for validation of SoC design
Multiple asynchronous clock domains have been increasingly employed in System-on-Chip (SoC) designs for different I/O interfaces. Functional validation is one of the most expensiv...
Yi Feng 0002, Zheng Zhou, Dong Tong, Xu Cheng
SRDS
1993
IEEE
15 years 1 months ago
Bayesian Analysis for Fault Location in Homogeneous Distributed Systems
We propose a simple and practical probabilistic comparison-based model, employing multiple incomplete test concepts, for handling fault location in distributed systems using a Bay...
Yu Lo Cyrus Chang, Leslie C. Lander, Horng-Shing L...
ET
2007
101views more  ET 2007»
14 years 9 months ago
Towards Nanoelectronics Processor Architectures
In this paper, we focus on reliability, one of the most fundamental and important challenges, in the nanoelectronics environment. For a processor architecture based on the unreliab...
Wenjing Rao, Alex Orailoglu, Ramesh Karri