377 search results - page 74 / 76 » Multiple Instruction Stream Processor |
152
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TJS
2002
15 years 1 months ago
2002
Historically, compilers have operated by applying a fixed set of optimizations in a predetermined order. We call such an ordered list of optimizations a compilation sequence. This...
131
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ISPDC
2010
IEEE
15 years 8 days ago
2010
IEEE
—Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi- ...
166
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TVLSI
2010
14 years 8 months ago
2010
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
111
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HPCA
2002
IEEE
16 years 2 months ago
2002
IEEE
Cyclops is a new architecture for high performance parallel computers being developed at the IBM T. J. Watson Research Center. The basic cell of this architecture is a single-chip...
139
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SIGMOD
2011
ACM
14 years 4 months ago
2011
ACM
An important means of allowing non-expert end-users to pose ad hoc queries — whether over single databases or data integration systems — is through keyword search. Given a set...