22193 search results - page 3864 / 4439 » Multiple Restricted Multiplication |
168
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ICCAD
2006
IEEE
16 years 3 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
157
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ICCAD
2005
IEEE
16 years 3 months ago
2005
IEEE
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...
159
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ICCAD
2003
IEEE
16 years 3 months ago
2003
IEEE
On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In deep sub-micron technology, the subthreshold leakage power is becoming...
188
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ICCAD
2002
IEEE
16 years 3 months ago
2002
IEEE
In this survey, we outline basic SAT- and ATPGprocedures as well as their applications in formal hardware verification. We attempt to give the reader a trace trough literature and...
122
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ICCAD
2002
IEEE
16 years 3 months ago
2002
IEEE
Design ECO commonly happens in industry due to constraints or target changes from manufacturing, marketing, reliability, or performance. At each step, designers usually want to mo...