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ISCA
2000
IEEE
105views Hardware» more  ISCA 2000»
15 years 9 months ago
Multiple-banked register file architectures
The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor genera...
José-Lorenzo Cruz, Antonio González,...
ISCA
2000
IEEE
107views Hardware» more  ISCA 2000»
15 years 9 months ago
A fully associative software-managed cache design
As DRAM access latencies approach a thousand instructionexecution times and on-chip caches grow to multiple megabytes, it is not clear that conventional cache structures continue ...
Erik G. Hallnor, Steven K. Reinhardt
128
Voted
ISCC
2000
IEEE
156views Communications» more  ISCC 2000»
15 years 9 months ago
Inverse Multiplexing for ATM. Technical Operation, Applications and Performance Evaluation Study
-- In a WAN established infrastructure, one of the main problems ATM network planners and users face, when greater than T1/E1 bandwidth is required, is the high cost associated to ...
Marcos Postigo-Boix, Mónica Aguilar-Igartua...
ISSRE
2000
IEEE
15 years 9 months ago
Evaluation of Regressive Methods for Automated Generation of Test Trajectories
Automated generation of test cases is a prerequisite for fast testing. Whereas the research has addressed the creation of individual test points, test trajectoiy generation has at...
Brian J. Taylor, Bojan Cukic
142
Voted
LICS
2000
IEEE
15 years 9 months ago
Concurrent Omega-Regular Games
We consider two-player games which are played on a finite state space for an infinite number of rounds. The games are concurrent, that is, in each round, the two players choose ...
Luca de Alfaro, Thomas A. Henzinger
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