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MICRO
2007
IEEE
129views Hardware» more  MICRO 2007»
15 years 11 months ago
A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy
Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed techniques for coherence traffic reduct...
Jason Zebchuk, Elham Safi, Andreas Moshovos
HPCA
2003
IEEE
16 years 5 months ago
A Statistically Rigorous Approach for Improving Simulation Methodology
Due to cost, time, and flexibility constraints, simulators are often used to explore the design space when developing a new processor architecture, as well as when evaluating the ...
Joshua J. Yi, David J. Lilja, Douglas M. Hawkins
156
Voted
CODES
2007
IEEE
15 years 11 months ago
Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC
Heterogeneous multiprocessors are emerging as the dominant implementation approach to embedded multiprocessor systems. In addition to having processing elements suited to the targ...
Brett H. Meyer, Donald E. Thomas
ICMCS
2006
IEEE
113views Multimedia» more  ICMCS 2006»
15 years 10 months ago
On Parallelization of a Video Mining System
As digital video data becomes more pervasive, mining information from multimedia data becomes increasingly important. Although researches in multimedia mining area have shown grea...
Wenlong Li, Eric Li, Nan Di, Carole Dulong, Tao Wa...
ACSC
2009
IEEE
15 years 11 months ago
ALARM: An Adaptive Load-Aware Routing Metric for Hybrid Wireless Mesh Networks
Abstract— Hybrid Wireless Mesh Networks (WMN) are generally employed to establish communication during disaster recovery operations. The Hybrid WMN network is formed in a spontan...
Asad Amir Pirzada, Ryan Wishart, Marius Portmann, ...