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ISCA
2000
IEEE
111views Hardware» more  ISCA 2000»
15 years 6 months ago
HLS: combining statistical and symbolic simulation to guide microprocessor designs
As microprocessors continue to evolve, many optimizations reach a point of diminishing returns. We introduce HLS, a hybrid processor simulator which uses statistical models and sy...
Mark Oskin, Frederic T. Chong, Matthew K. Farrens
SOSP
1989
ACM
15 years 3 months ago
Performance of Firefly RPC
In this paper, we report on the performance of the remote procedure call implementation for the Firefly multiprocessor and analyze the implementation to account precisely for all ...
Michael D. Schroeder, Michael Burrows
PLDI
2012
ACM
13 years 4 months ago
Effective parallelization of loops in the presence of I/O operations
Software-based thread-level parallelization has been widely studied for exploiting data parallelism in purely computational loops to improve program performance on multiprocessors...
Min Feng, Rajiv Gupta, Iulian Neamtiu
DATE
2009
IEEE
132views Hardware» more  DATE 2009»
15 years 8 months ago
Power and performance of read-write aware Hybrid Caches with non-volatile memories
—Caches made of non-volatile memory technologies, such as Magnetic RAM (MRAM) and Phase-change RAM (PRAM), offer dramatically different power-performance characteristics when com...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Yu...
ESTIMEDIA
2008
Springer
15 years 3 months ago
Performance analysis of reconfiguration in adaptive real-time streaming applications
We propose a design optimization framework for adaptive real-time streaming applications. The main contribution is a hybrid approach for performance analysis combining formal anal...
Jun Zhu, Ingo Sander, Axel Jantsch