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ICCD
2003
IEEE
115views Hardware» more  ICCD 2003»
16 years 1 months ago
Reducing Compilation Time Overhead in Compiled Simulators
Compiled simulation is a well known technique for improving the performance of instruction set simulators at the cost of compilation time. However the compilation time overhead ma...
Mehrdad Reshadi, Nikil D. Dutt
152
Voted
DAC
2010
ACM
15 years 4 months ago
QuickYield: an efficient global-search based parametric yield estimation with performance constraints
With technology scaling down to 90nm and below, many yield-driven design and optimization methodologies have been proposed to cope with the prominent process variation and to incr...
Fang Gong, Hao Yu, Yiyu Shi, Daesoo Kim, Junyan Re...
CF
2006
ACM
15 years 10 months ago
Dynamic thread assignment on heterogeneous multiprocessor architectures
In a multi-programmed computing environment, threads of execution exhibit different runtime characteristics and hardware resource requirements. Not only do the behaviors of distin...
Michela Becchi, Patrick Crowley
GLOBECOM
2008
IEEE
15 years 10 months ago
Numerical Performance Evaluation of OFDM Systems Affected by Transmitter Nonlinearities, Phase Noise and Channel Estimation Erro
Abstract—In this contribution we present a numerical approach to evaluate the bit error rate and mutual information of OFDM links affected by transmitter nonlinearities, phase no...
Steffen Bittner, Marco Krondorf, Gerhard Fettweis
PADS
1999
ACM
15 years 8 months ago
Performance Prediction Tools for Parallel Discrete-Event Simulation
We have developed a set of performance prediction tools which help to estimate the achievable speedups from parallelizing a sequential simulation. The tools focus on two important...
Chu-Cheow Lim, Yoke-Hean Low, Boon-Ping Gan, Sanja...