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ISCA
2010
IEEE
222views Hardware» more  ISCA 2010»
15 years 6 months ago
Cohesion: a hybrid memory model for accelerators
Two broad classes of memory models are available today: models with hardware cache coherence, used in conventional chip multiprocessors, and models that rely upon software to mana...
John H. Kelm, Daniel R. Johnson, William Tuohy, St...
ESANN
2003
15 years 5 months ago
Accelerating the convergence speed of neural networks learning methods using least squares
In this work a hybrid training scheme for the supervised learning of feedforward neural networks is presented. In the proposed method, the weights of the last layer are obtained em...
Oscar Fontenla-Romero, Deniz Erdogmus, José...
HPCA
2000
IEEE
15 years 8 months ago
Coherence Communication Prediction in Shared-Memory Multiprocessors
Abstract—Sharing patterns in shared-memory multiprocessors are the key to performance: uniprocessor latencytolerating techniques such as out-of-order execution and non-blocking c...
Stefanos Kaxiras, Cliff Young
141
Voted
ISCA
2011
IEEE
225views Hardware» more  ISCA 2011»
14 years 7 months ago
FlexBulk: intelligently forming atomic blocks in blocked-execution multiprocessors to minimize squashes
Blocked-execution multiprocessor architectures continuously run atomic blocks of instructions — also called Chunks. Such architectures can boost both performance and software pr...
Rishi Agarwal, Josep Torrellas
DATE
2009
IEEE
133views Hardware» more  DATE 2009»
15 years 11 months ago
Energy efficient multiprocessor task scheduling under input-dependent variation
— In this paper, we propose a novel, energy aware scheduling algorithm for applications running on DVS-enabled multiprocessor systems, which exploits variation in execution times...
Jason Cong, Karthik Gururaj