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HPCA
2009
IEEE
16 years 4 months ago
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
Reetuparna Das, Soumya Eachempati, Asit K. Mishra,...
TMM
2002
94views more  TMM 2002»
15 years 3 months ago
A jointly optimal fractal/DCT compression scheme
In this paper a hybrid fractal and Discrete Cosine transform (DCT) coder is developed. Drawing on the ability of DCT to remove inter-pixel redundancies and on the ability of fracta...
Gerry Melnikov, Aggelos K. Katsaggelos
ISCAS
2007
IEEE
122views Hardware» more  ISCAS 2007»
15 years 10 months ago
Neuromimetic ICs with analog cores: an alternative for simulating spiking neural networks
- This paper aims at discussing the implementation of simulation systems for SNN based on analog computation cores (neuromimetic ICs). Such systems are an alternative to completely...
Sylvie Renaud, Jean Tomas, Yannick Bornat, Adel Da...
DAC
2009
ACM
16 years 5 months ago
Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis
In this paper, a design method for automotive architectures is proposed. The two main technical contributions are (i) a novel hardware/software architecture encoding that unifies ...
Jürgen Teich, Martin Lukasiewycz, Michael Gla...
GLVLSI
2006
IEEE
98views VLSI» more  GLVLSI 2006»
15 years 10 months ago
Rapid intermodulation distortion estimation in fully balanced weakly nonlinear Gm-C filters using state-space modeling
State-space modeling of fully differential Gm-C filters with weak nonlinearities is used to develop a fast algorithm for intermodulation distortion estimation. It results in sim...
Paul Sotiriadis, Abdullah Celik, Zhaonian Zhang