Sciweavers

5190 search results - page 201 / 1038
» Multithreaded Parallel Computer Model with Performance Evalu...
Sort
View
HPDC
1999
IEEE
15 years 2 months ago
An Evaluation of Linear Models for Host Load Prediction
This paper evaluates linear models for predicting the Digital Unix five-second load average from 1 to 30 seconds into the future. A detailed statistical study of a large number of...
Peter A. Dinda, David R. O'Hallaron
IPPS
1999
IEEE
15 years 2 months ago
Non-Preemptive Scheduling of Real-Time Threads on Multi-Level-Context Architectures
The rapid progress in high-performance microprocessor design has made it di cult to adapt real-time scheduling results to new models of microprocessor hardware, thus leaving an un...
Jan Jonsson, Henrik Lönn, Kang G. Shin
97
Voted
IPPS
2002
IEEE
15 years 3 months ago
Memory-Intensive Benchmarks: IRAM vs. Cache-Based Machines
The increasing gap between processor and memory performance has led to new architectural models for memory-intensive applications. In this paper, we use a set of memory-intensive ...
Brian R. Gaeke, Parry Husbands, Xiaoye S. Li, Leon...
EUROPAR
1995
Springer
15 years 1 months ago
Relating Data-Parallelism and (And-) Parallelism in Logic Programs
Much work has been done in the areas of and–parallelism and data parallelism in Logic Programs. Such work has proceeded to a certain extent in an independent fashion. Both types...
Manuel V. Hermenegildo, Manuel Carro
VLSID
2001
IEEE
200views VLSI» more  VLSID 2001»
15 years 10 months ago
Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures
The emergence of several communication architectures for System-on-Chips provides designers with a variety of design alternatives. In addition, the need to customize the system ar...
Kanishka Lahiri, Sujit Dey, Anand Raghunathan