Sciweavers

5190 search results - page 209 / 1038
» Multithreaded Parallel Computer Model with Performance Evalu...
Sort
View
HPCA
2007
IEEE
15 years 10 months ago
HARD: Hardware-Assisted Lockset-based Race Detection
The emergence of multicore architectures will lead to an increase in the use of multithreaded applications that are prone to synchronization bugs, such as data races. Software sol...
Pin Zhou, Radu Teodorescu, Yuanyuan Zhou
IPPS
1999
IEEE
15 years 2 months ago
The Paderborn University BSP (PUB) Library - Design, Implementation and Performance
The Paderborn University BSP (PUB) library is a parallel C library based on the BSP model. The basic library supports buffered and unbuffered asynchronous communication between an...
Olaf Bonorden, Ben H. H. Juurlink, Ingo von Otte, ...
IPPS
2008
IEEE
15 years 4 months ago
Early experience with out-of-core applications on the Cray XMT
This paper describes our early experiences with a preproduction Cray XMT system that implements a scalable shared memory architecture with hardware support for multithreading. Unl...
Daniel G. Chavarría-Miranda, Andrès ...
HPCC
2007
Springer
15 years 2 months ago
An Exploration of Performance Attributes for Symbolic Modeling of Emerging Processing Devices
Vector, emerging (homogenous and heterogeneous) multi-core and a number of accelerator processing devices potentially offer an order of magnitude speedup for scientific application...
Sadaf R. Alam, Nikhil Bhatia, Jeffrey S. Vetter
ICPP
1991
IEEE
15 years 1 months ago
Two Techniques to Enhance the Performance of Memory Consistency Models
The memory consistency model supported by a multiprocessor directly affects its performance. Thus, several attempts have been made to relax the consistency models to allow for mor...
Kourosh Gharachorloo, Anoop Gupta, John L. Henness...