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HPCA
2009
IEEE
16 years 3 months ago
Adaptive Spill-Receive for robust high-performance caching in CMPs
In a Chip Multi-Processor (CMP) with private caches, the last level cache is statically partitioned between all the cores. This prevents such CMPs from sharing cache capacity in r...
Moinuddin K. Qureshi
ICS
2005
Tsinghua U.
15 years 8 months ago
Low-power, low-complexity instruction issue using compiler assistance
In an out-of-order issue processor, instructions are dynamically reordered and issued to function units in their dataready order rather than their original program order to achiev...
Madhavi Gopal Valluri, Lizy Kurian John, Kathryn S...
CCGRID
2010
IEEE
15 years 4 months ago
Elastic Site: Using Clouds to Elastically Extend Site Resources
Infrastructure-as-a-Service (IaaS) cloud computing offers new possibilities to scientific communities. One of the most significant is the ability to elastically provision and relin...
Paul Marshall, Kate Keahey, Timothy Freeman
SIGMETRICS
2011
ACM
229views Hardware» more  SIGMETRICS 2011»
14 years 5 months ago
Model-driven optimization of opportunistic routing
Opportunistic routing aims to improve wireless performance by exploiting communication opportunities arising by chance. A key challenge in opportunistic routing is how to achieve ...
Eric Rozner, Mi Kyung Han, Lili Qiu, Yin Zhang
SPAA
2010
ACM
15 years 8 months ago
Transactions in the jungle
Transactional memory (TM) has shown potential to simplify the task of writing concurrent programs. Inspired by classical work on databases, formal definitions of the semantics of...
Rachid Guerraoui, Thomas A. Henzinger, Michal Kapa...