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HPCA
2006
IEEE
15 years 10 months ago
BulletProof: a defect-tolerant CMP switch architecture
As silicon technologies move into the nanometer regime, transistor reliability is expected to wane as devices become subject to extreme process variation, particle-induced transie...
Kypros Constantinides, Stephen Plaza, Jason A. Blo...
DSN
2004
IEEE
15 years 1 months ago
The Recursive NanoBox Processor Grid: A Reliable System Architecture for Unreliable Nanotechnology Devices
Advanced molecular nanotechnology devices are expected to have exceedingly high transient fault rates and large numbers of inherent device defects compared to conventional CMOS de...
A. J. KleinOsowski, Kevin KleinOsowski, Vijay Rang...
HPCA
2009
IEEE
15 years 10 months ago
A novel architecture of the 3D stacked MRAM L2 cache for CMPs
Magnetic Random Access Memory (MRAM) is considered to be a promising future memory technology due to its low leakage power, high density and fast read speed. The heterogeneous int...
Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yira...
ICDCSW
2005
IEEE
15 years 3 months ago
Control Theory Optimization of MECN in Satellite Networks
Congestion in the Internet results in wasted bandwidth and also stands in the way of guaranteeing QoS. The effect of congestion is multiplied many fold in Satellite networks, wher...
Arjan Durresi, Mukundan Sridharan, Sriram Chellapp...
DATE
2008
IEEE
182views Hardware» more  DATE 2008»
15 years 4 months ago
A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking
— As the feature size of transistors gets smaller, fabricating them becomes challenging. Manufacturing process follows various corrective design-for-manufacturing (DFM) steps to ...
Swaroop Ghosh, Patrick Ndai, Kaushik Roy