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IPPS
2006
IEEE
15 years 3 months ago
A compiler-based communication analysis approach for multiprocessor systems
In this paper we describe a compiler framework which can identify communication patterns for MPIbased parallel applications. This has the potential of providing significant perfo...
Shuyi Shao, Alex K. Jones, Rami G. Melhem
IPPS
2002
IEEE
15 years 2 months ago
Memory-Intensive Benchmarks: IRAM vs. Cache-Based Machines
The increasing gap between processor and memory performance has led to new architectural models for memory-intensive applications. In this paper, we use a set of memory-intensive ...
Brian R. Gaeke, Parry Husbands, Xiaoye S. Li, Leon...
ISCA
1994
IEEE
117views Hardware» more  ISCA 1994»
15 years 1 months ago
Evaluating Stream Buffers as a Secondary Cache Replacement
Today's commodity microprocessors require a low latency memory system to achieve high sustained performance. The conventional high-performance memory system provides fast dat...
Subbarao Palacharla, Richard E. Kessler
SP
2008
IEEE
138views Security Privacy» more  SP 2008»
14 years 9 months ago
A performance tuning methodology with compiler support
We have developed an environment, based upon robust, existing, open source software, for tuning applications written using MPI, OpenMP or both. The goal of this effort, which inte...
Oscar Hernandez, Barbara M. Chapman, Haoqiang Jin
57
Voted
HICSS
1996
IEEE
86views Biometrics» more  HICSS 1996»
15 years 1 months ago
Towards a Thread-Based Parallel Direct Execution Simulator
Parallel direct execution simulation is an important tool for performance and scalability analysis of large message passing parallel programs executing on top of a virtual compute...
Phillip M. Dickens, Matthew Haines, Piyush Mehrotr...