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MICRO
2005
IEEE
130views Hardware» more  MICRO 2005»
15 years 5 months ago
Exploiting Vector Parallelism in Software Pipelined Loops
An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
Samuel Larsen, Rodric M. Rabbah, Saman P. Amarasin...
JEA
1998
133views more  JEA 1998»
14 years 11 months ago
A New Deterministic Parallel Sorting Algorithm with an Experimental Evaluation
We introduce a new deterministic parallel sorting algorithm based on the regular sampling approach. The algorithm uses only two rounds of regular all-to-all personalized communica...
David R. Helman, Joseph JáJá, David ...
DASFAA
2010
IEEE
179views Database» more  DASFAA 2010»
15 years 6 months ago
Scalable Splitting of Massive Data Streams
Scalable execution of continuous queries over massive data streams often requires splitting input streams into parallel sub-streams over which query operators are executed in paral...
Erik Zeitler, Tore Risch
HPCA
2008
IEEE
16 years 6 days ago
An OS-based alternative to full hardware coherence on tiled CMPs
The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling...
Christian Fensch, Marcelo Cintra
IEEEPACT
2000
IEEE
15 years 4 months ago
Neighborhood Prefetching on Multiprocessors Using Instruction History
A multiprocessor prefetch scheme is described in which a miss is followed by a prefetch of a group of lines, a neighborhood, surrounding the demand-fetched line. The neighborhood ...
David M. Koppelman