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ASPLOS
2012
ACM
13 years 7 months ago
Aikido: accelerating shared data dynamic analyses
Despite a burgeoning demand for parallel programs, the tools available to developers working on shared-memory multicore processors have lagged behind. One reason for this is the l...
Marek Olszewski, Qin Zhao, David Koh, Jason Ansel,...
DATE
2009
IEEE
98views Hardware» more  DATE 2009»
15 years 6 months ago
A real-time application design methodology for MPSoCs
This paper presents a novel technique for the modeling, simulation, and analysis of real-time applications on MultiProcessor Systems-on-Chip (MPSoCs). This technique is based on a...
Giovanni Beltrame, Luca Fossati, Donatella Sciuto
DATE
2008
IEEE
86views Hardware» more  DATE 2008»
15 years 6 months ago
Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs
Abstract—Wafer-level test during burn-in (WLTBI) has recently emerged as a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, the testi...
Sudarshan Bahukudumbi, Krishnendu Chakrabarty, Ric...
ISORC
2008
IEEE
15 years 6 months ago
Usability Aspects of WCET Analysis
Knowing the program timing characteristics is fundamental to the successful design and execution of real-time systems. A critical timing measure is the worst-case execution time (...
Jan Gustafsson
DATE
2005
IEEE
119views Hardware» more  DATE 2005»
15 years 5 months ago
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips
Multi-site testing is a popular and effective way to increase test throughput and reduce test costs. We present a test throughput model, in which we focus on wafer testing, and co...
Sandeep Kumar Goel, Erik Jan Marinissen