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VLSID
1998
IEEE
116views VLSI» more  VLSID 1998»
15 years 3 months ago
Synthesis of Testable RTL Designs
With several commercial tools becoming available, the high-level synthesis of applicationspeci c integrated circuits is nding wide spread acceptance in VLSI industry today. Existi...
C. P. Ravikumar, Sumit Gupta, Akshay Jajoo
DAC
2007
ACM
16 years 2 days ago
Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits
Despite the impressive progress of logic synthesis in the past decade, finding the best architecture for a given circuit still remains an open problem and largely unsolved. In mos...
Ajay K. Verma, Philip Brisk, Paolo Ienne
ICCAD
1994
IEEE
117views Hardware» more  ICCAD 1994»
15 years 3 months ago
Optimization of critical paths in circuits with level-sensitive latches
A simple extension of the critical path method is presented which allows more accurate optimization of circuits with level-sensitive latches. The extended formulation provides a s...
Timothy M. Burks, Karem A. Sakallah
TCAD
2008
81views more  TCAD 2008»
14 years 11 months ago
Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring
The relatively poor scaling of interconnect in modern digital circuits necessitates a number of design optimizations, which must typically be iterated several times to meet the spe...
Stephen Plaza, Igor L. Markov, Valeria Bertacco
ICES
2003
Springer
86views Hardware» more  ICES 2003»
15 years 4 months ago
A Note on Designing Logical Circuits Using SAT
Abstract. We present a systematic procedure for the synthesis and minimisation of digital circuits using propositional satisfiability. We encode the truth table into a canonical s...
Giovani Gomez Estrada