84 search results - page 6 / 17 » NBTI-Aware Synthesis of Digital Circuits |
ASPDAC
2001
ACM
15 years 2 months ago
2001
ACM
Asynchronous, self-timed, logic is often eschewed in digital design because of its ad-hoc methodologies and lack of available design tools. This paper describes a complete High Le...
105
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WCE
2007
15 years 7 days ago
2007
Improving testability during the early stages of High-level synthesis has several advantages including reduced test hardware overhead and design iterations. Recently, BIST techniq...
EH
2003
IEEE
15 years 4 months ago
2003
IEEE
This paper describes a multi-objective Evolutionary Algorithm (EA) system for the synthesis of efficient non-linear VLSI circuit modules. The EA takes the specification for a no...
109
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INTEGRATION
2006
14 years 11 months ago
2006
Improving testability during the early stages of high-level synthesis has several benefits including reduced test hardware overheads, reduced test costs, reduced design iterations...
FPL
2010
Springer
14 years 9 months ago
2010
Springer
This paper presents a novel IP core reuse strategy which reduces design time from days to hours for communication circuits such as digital radio receivers. This design productivity...