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» NOC architecture design for multi-cluster chips
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DAC
2008
ACM
15 years 10 months ago
On reliable modular testing with vulnerable test access mechanisms
In modular testing of system-on-a-chip (SoC), test access mechanisms (TAMs) are used to transport test data between the input/output pins of the SoC and the cores under test. Prio...
Lin Huang, Feng Yuan, Qiang Xu
HPCA
2008
IEEE
15 years 10 months ago
Regional congestion awareness for load balance in networks-on-chip
Interconnection networks-on-chip (NOCs) are rapidly replacing other forms of interconnect in chip multiprocessors and system-on-chip designs. Existing interconnection networks use...
Paul Gratz, Boris Grot, Stephen W. Keckler