75 search results - page 12 / 15 » Near-memory Caching for Improved Energy Consumption |
126
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WINET
2011
14 years 4 months ago
2011
During the last decade, Wireless Sensor Networks (WSNs) have emerged and matured at such point that currently support several applications like environment control, intelligent bu...
PDP
2010
IEEE
15 years 1 months ago
2010
IEEE
In the last years high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures that implement multiple processing cores on a single die. As the nu...
116
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TVLSI
2010
14 years 4 months ago
2010
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
102
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ASPLOS
2010
ACM
15 years 24 days ago
2010
ACM
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...
ISCA
2010
IEEE
15 years 2 months ago
2010
IEEE
DRAM vendors have traditionally optimized the cost-perbit metric, often making design decisions that incur energy penalties. A prime example is the overfetch feature in DRAM, wher...